Owing to the rapid development of the mobile communication industry, the demand for radio frequency integrated circuits (RFIC) has increased tremendously and the RFIC technology filed is getting very competitive. BiCMOS, refers to the integration of bipolar junction transistors and CMOS technology into a single integrated circuit device, is widely used and has been quiet successful in the RFIC technology filed with high density and the advantages both of BJT and CMOS. As CMOS adopts the thin silicon-on-insulator (SOI) substrate for lower power and higher speed, SOI BiCOMS has caught worldwide attention.
In order to facilitate integration with SOI CMOS, lateral SOI BJTs have been proposed and studied. Even though lateral SOI BJT devices are easier to be integrated with SOI CMOS, the performance of such devices is limited. This is because the base width in the lateral SOI BJT is determined by lithography. However, the base width has a direct effect on transistor gain, thereby influencing the DC characteristics of the transistor. On the other hand, the carrier transit time is directly related to the base width, and the transistor cutoff frequency varies inversely as carrier transit time, therefore the base width has a great impact on frequency characteristic of the transistor. In a word, the base width has great influence on the transistor characteristics, and the lateral SOI BJT devices cannot be easily scaled down.
Compared with the lateral SOI BJT, a vertical SOI BJT is another type of SOI BJT. In the conventional vertical SOI BJT, the bulk silicon BJT technology is applied to SOI substrate, thereby such a BJT is unsuitable for the integration with high-performance SOI CMOS. There are two problems: On the one hand, the shallow trench isolation technology is very complicated and thereby increases the integration cost; On the other hand, the extraction electrode with ohmic contact formed by high dose rate ion implantation raises the area, and thereby lower the density of integration. At present, there is a new type of SOI BJT, which adopts back gate-induced, minority carrier inversion layer as collector. Although it can improve the integration of SOI BJT and high-performance SOI CMOS, for a typical SOI substrate, a substrate bias of 30 V is required in order to pass through the back-gate and form inversion layer in the body region of SOI. Such a high bias is not compatible with conventional SOI CMOS techniques, thus the buried oxide layer of the SOI BJT active region has to be thinned and a graphical SOI substrate is required. However, there are two problems adopting the graphical SOI substrate: (1) it is hard to be aligned in photolithography; (2) it makes the SOI BJT manufacturing process more complicated.